The secret to AMD Zen5’s 40% performance jump: a big upgrade to the exclusive AVX-512 instruction set

It was previously claimed that the theoretical single-core performance of the AMD Zen5 architecture could be boosted by more than 40% compared to Zen4, which is quite incredible, and according to MLID's latest claims, the secret should come from the AVX-512 instruction set.

AVX-512 instruction set was originally Intel's unique secret, AMD Zen4 architecture began to support, including consumer-grade RuiLong, data center-grade EPYC, and the embarrassing thing is that Intel, because of the use of large and small-core architectural design, next-generation Arrow Lake, Lunar Lake, a high probability that no longer support AVX-512 (and also no Hyper-Threading), and in turn, become AMD exclusive.

The AVX-512 instruction set of the Zen4 architecture is executed in combination with two 256-bit FPU floating point units, which can be a bit more flexible and consume less power, but the performance is not as extreme as it could be.

The Zen5 architecture will introduce a 512-bit FPU unit that can directly execute AVX-512 for better performance, as well as efficiently execute instructions such as VNNI, which is more conducive to improving AI performance.

To this end, the Zen5 architecture will also be upgraded to match in other areas to facilitate feeding the FPU unit enough data and instructions.

For example, the first-level cache DTLB is increased, the first-level data cache capacity is increased from 32KB to 48KB, for example, the load memory queue is widened, for example, the FPU MADD delay is shortened by one clock cycle, and so on.

In addition, the Zen5 architecture's integer execution pipeline will be increased from 8 to 10.

However, the L2 cache capacity remains the same, still 1MB per core.