Breakthrough in von Neumann architecture bottleneck, China develops smallest size phase change memory cell

According to the Shanghai Institute of Microsystems and Information Technology (SIMIT) of the Chinese Academy of Sciences (CAS), a joint research team consisting of researcher Zhitang Song and Haomin Wang has prepared the world's smallest size phase change memory cell device for the first time using GNR edge-contact.

Via http://www.sim.cas.cn/xwzx2016/kyjz/202207/t20220722_6489179.html

On July 18, the research results, titled "Minimizing the programming power of phase change memory by using graphene nanoribbon edge-contact," were published online in Advanced Science. The paper was published online in Advanced Science.

It is understood that the traditional von Neumann computing architecture has become a major technical obstacle to continue improving the performance of computing systems in the future due to the explosive growth of data production today.

Phase change random access memory (PCRAM), which can combine storage and computational functions, is an ideal pathway option to break the bottleneck of the von Neumann computing architecture.

PCRAM has the advantages of non-volatility, fast programming speed and long cycle life, but the large contact area between the phase change material and the heating electrode in it causes high power consumption for phase change memory operation, and how to further reduce the power consumption becomes one of the biggest challenges for the future development of phase change memory.

The research team uses graphene boundary as a blade electrode to contact the phase change material, which can achieve a cycle life of more than 10,000 times.

When the GNR width is reduced to 3 nm with a cross-sectional area of 1 nm2, the RESET current is reduced to 0.9 μA and the write energy consumption is as low as ~53.7 fJ. This power consumption is nearly two orders of magnitude lower than that of a single component prepared by the current state-of-the-art process, and is almost half of the original world record for minimum power consumption held by carbon nanotube cleavage (CNT-gap).

According to the Chinese Academy of Sciences, this is the first international high-performance phase change memory cell with extreme size achieved by GNR edge contact, and the device size is close to the scaling limit of phase change memory technology. The successful development of this new phase-change memory cell represents an advancement in the execution of logic operations in PCRAM at low power consumption, opening up a new technological path for future memory computing.

The world's smallest size phase change memory cell device is prepared by using GNR edge contact (a) schematic diagram of phase change memory cell structure; (b) power consumption versus contact area.

Bias polarity dependence of device cycle life. (a) Schematic of the measurement setup; (b) cycling lifetime of ~3 nm wide GNR boundary electrode phase change memory cell at different voltage polarities.

Demonstration of D-type flip-flop logic function based on 3 nm wide GNR boundary electrode. (a) schematic diagram of D-type flip-flop structure; (b) transfer characteristic curve when the device is in high/low resistance state; (c) device cyclic characteristic; (d) GNR boundary contact-based phase-change memory cell demonstrating the logic timing of D-type flip-flop.